Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 6823500 | 2-dimensional placement with reliability constraints for VLSI design | Kiran Ganesh, Miles F. Mccoo, Naresh Sehgal | 2004-11-23 | $26,666,000 |
| 6658631 | Method and system for dynamically generating resistance, capacitance, and delay table look-ups | Iksoo Pyo | 2003-12-02 | $54,763,000 |