| 7268591 |
Decode structure with parallel rotation |
Jan-Michael Huber |
2007-09-11 |
| 5592426 |
Extended segmented precharge architecture |
Derwin Jallice, Christopher M. Durham |
1997-01-07 |
| 5566130 |
Address transition detection (ATD) circuit for asynchronous VLSI chips |
Christopher M. Durham, Craig L. Stephen |
1996-10-15 |
| 5301165 |
Chip select speedup circuit for a memory |
Christopher M. Durham, Derwin Jallice |
1994-04-05 |
| 5146111 |
Glitch-proof powered-down on chip receiver with non-overlapping outputs |
Christopher M. Durham, Derwin Jallice |
1992-09-08 |
| 4996670 |
Zero standby power, radiation hardened, memory redundancy circuit |
Christopher M. Durham, Derwin Jallice |
1991-02-26 |
| 4969125 |
Asynchronous segmented precharge architecture |
Christopher M. Durham, Reginald E. Harrison, Derwin J. Jallice, Dave C. Lawson, Craig L. Stephen |
1990-11-06 |
