Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5974245 | Method and apparatus for making integrated circuits by inserting buffers into a netlist | Ying Li, Sunil Ashtaputre, Jacob Greidinger, Moazzem Hossain, Siu-Tong Hui | 1999-10-26 |
| 5856927 | Method for automatically routing circuits of very large scale integration (VLSI) | Jacob Greidinger, Ara Markosian, Christine Fawcett, Eugenia Gelfund, Prasad Sakhamuri | 1999-01-05 |
| RE35671 | Predictive capacitance layout method for integrated circuits | — | 1997-11-25 |
| 5638291 | Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew | Ying Li, Sunil Ashtaputre, Jacob Greidinger, Moazzem Hossain, Siu-Tong Hui | 1997-06-10 |
| 5521836 | Method for determining instance placements in circuit layouts | James A. Rowson | 1996-05-28 |
| 5399517 | Method of routing three layer metal gate arrays using a channel router | Sunil Ashtaputre, Kieu Do, Prasad Sakhamuri, Charles H Ng | 1995-03-21 |
| 5367469 | Predictive capacitance layout method for integrated circuits | — | 1994-11-22 |
| 5313079 | Gate array bases with flexible routing | Daniel Brasen, James D. Shiffer, II, Sunil Asktaputre | 1994-05-17 |
| 5295088 | Method for predicting capacitance of connection nets on an integrated circuit | Robert D. Shur | 1994-03-15 |
| 5197015 | System and method for setting capacitive constraints on synthesized logic circuits | Thomas J. Schaefer, Robert D. Shur | 1993-03-23 |
| 5193092 | Integrated parity-based testing for integrated circuits | James A. Rowson, Robert D. Shur, Kenneth D. Van Egmond | 1993-03-09 |