| 9761029 |
Display three-dimensional object on browser |
Prakash Reddy, Deivanayagam RAMAKRISHNAN |
2017-09-12 |
| 7424703 |
Method and system for simulation of mixed-language circuit designs |
Edwin A. Harcourt, Koushik Roy, Doug Dunlop, Stuart Rae, Tuay-Ling Kathy Lang +2 more |
2008-09-09 |
| 5956257 |
Automated optimization of hierarchical netlists |
Arnold Ginetti, Thomas J. Schaefer, Christopher H. Kingsley |
1999-09-21 |
| 5787010 |
Enhanced dynamic programming method for technology mapping of combinational logic circuits |
Thomas J. Schaefer |
1998-07-28 |
| 5483544 |
Vector-specific testability circuitry |
— |
1996-01-09 |
| 5402357 |
System and method for synthesizing logic circuits with timing constraints |
Thomas J. Schaefer |
1995-03-28 |
| 5402356 |
Buffer circuit design using back track searching of site trees |
Thomas J. Schaefer |
1995-03-28 |
| 5295088 |
Method for predicting capacitance of connection nets on an integrated circuit |
Mark R. Hartoog |
1994-03-15 |
| 5272651 |
Circuit simulation system with wake-up latency |
Steve Bush |
1993-12-21 |
| 5197015 |
System and method for setting capacitive constraints on synthesized logic circuits |
Mark R. Hartoog, Thomas J. Schaefer |
1993-03-23 |
| 5193092 |
Integrated parity-based testing for integrated circuits |
Mark R. Hartoog, James A. Rowson, Kenneth D. Van Egmond |
1993-03-09 |
| 5068812 |
Event-controlled LCC stimulation |
Thomas J. Schaefer |
1991-11-26 |
| 5062067 |
Levelized logic simulator with fenced evaluation |
Thomas J. Schaefer |
1991-10-29 |