| 10872050 |
Bit-mapped DMA transfer with dependency table configured to monitor channel between DMA and array of bits to indicate a completion of DMA transfer |
Cyrill C. Ponce, Gianico G. Noble |
2020-12-22 |
| 10540242 |
Adaptive power cycle sequences for data recovery |
Rolando H. Bruce, Richard A. Cantong |
2020-01-21 |
| 10372643 |
Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system |
Cyrill C. Ponce, Gianico G. Noble |
2019-08-06 |
| 10180887 |
Adaptive power cycle sequences for data recovery |
Rolando H. Bruce, Richard A. Cantong |
2019-01-15 |
| 10042799 |
Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system |
Cyrill C. Ponce, Gianico G. Noble |
2018-08-07 |
| 9934160 |
Bit-mapped DMA and IOC transfer with dependency table comprising plurality of index fields in the cache for DMA transfer |
Cyrill C. Ponce, Gianico G. Noble |
2018-04-03 |
| 9672178 |
Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system |
Cyrill C. Ponce, Gianico G. Noble |
2017-06-06 |
| 9400617 |
Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained |
Cyrill C. Ponce, Gianico G. Noble |
2016-07-26 |
| 9372755 |
Adaptive power cycle sequences for data recovery |
Rolando H. Bruce, Richard A. Cantong |
2016-06-21 |
| 8165301 |
Input-output device and storage controller handshake protocol using key exchange for data security |
Rey H. Bruce, Raquel Bautista David |
2012-04-24 |