RB

Rolando H. Bruce

BN Bitmicro Networks: 8 patents #4 of 57Top 8%
BI Bitmicro: 5 patents #2 of 24Top 9%
BM Bit Microsystems: 3 patents #2 of 6Top 35%
Overall (All Time): #294,744 of 4,157,543Top 8%
16
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10540242 Adaptive power cycle sequences for data recovery Richard A. Cantong, Marizonne O. Fuentes 2020-01-21
10445239 Write buffering Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera 2019-10-15
10210084 Multi-leveled cache management in a hybrid storage system Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera 2019-02-19
10180887 Adaptive power cycle sequences for data recovery Richard A. Cantong, Marizonne O. Fuentes 2019-01-15
10082966 Electronic storage device Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian Alcid Arcedera, Ryan C. Chong 2018-09-25
9734067 Write buffering Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera 2017-08-15
9484103 Electronic storage device Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian Alcid Arcedera, Ryan C. Chong 2016-11-01
9430386 Multi-leveled cache management in a hybrid storage system Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera 2016-08-30
9372755 Adaptive power cycle sequences for data recovery Richard A. Cantong, Marizonne O. Fuentes 2016-06-21
9099187 Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian Alcid Arcedera, Ryan C. Chong 2015-08-04
8560804 Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian Alcid Arcedera, Ryan C. Chong 2013-10-15
6970890 Method and apparatus for data recovery Ricardo H. Bruce 2005-11-29
6529416 Parallel erase operations in memory systems Ricardo H. Bruce 2003-03-04
6000006 Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage Ricardo H. Bruce, Earl T. Cohen, Allan Christie 1999-12-07
5956743 Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations Ricardo H. Bruce, Earl T. Cohen 1999-09-21
5822251 Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers Ricardo H. Bruce, Earl T. Cohen 1998-10-13