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Bit-mapped DMA transfer with dependency table configured to monitor channel between DMA and array of bits to indicate a completion of DMA transfer |
Marizonne O. Fuentes, Gianico G. Noble |
2020-12-22 |
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Bus arbitration with routing and failover mechanism |
Ricardo H. Bruce, Jarmie Dela Cruz Espuerta, Marlon B. Verdan |
2019-10-01 |
| 10423554 |
Bus arbitration with routing and failover mechanism |
Ricardo H. Bruce, Jarmie Dela Cruz Espuerta |
2019-09-24 |
| 10372643 |
Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system |
Marizonne O. Fuentes, Gianico G. Noble |
2019-08-06 |
| 10042799 |
Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system |
Marizonne O. Fuentes, Gianico G. Noble |
2018-08-07 |
| 9934160 |
Bit-mapped DMA and IOC transfer with dependency table comprising plurality of index fields in the cache for DMA transfer |
Marizonne O. Fuentes, Gianico G. Noble |
2018-04-03 |
| 9916213 |
Bus arbitration with routing and failover mechanism |
Ricardo H. Bruce, Jarmie De La Cruz Espuerta, Marlon B. Verdan |
2018-03-13 |
| 9798688 |
Bus arbitration with routing and failover mechanism |
Ricardo H. Bruce, Jarmie Dela Cruz Espuerta |
2017-10-24 |
| 9672178 |
Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system |
Marizonne O. Fuentes, Gianico G. Noble |
2017-06-06 |
| 9400617 |
Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained |
Marizonne O. Fuentes, Gianico G. Noble |
2016-07-26 |