Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5412787 | Two-level TLB having the second level TLB implemented in cache tag RAMs | Patrick Knebel | 1995-05-02 |
| 5396604 | System and method for reducing the penalty associated with data cache misses | Eric Delano | 1995-03-07 |
| 5337415 | Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency | Eric Delano, Craig A. Gleason | 1994-08-09 |
| 5327566 | Stage saving and restoring hardware mechanism | — | 1994-07-05 |