LC

Lance Cheney

IN Intel: 11 patents #3,700 of 30,777Top 15%
Overall (All Time): #404,158 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12141890 Enabling product SKUs based on chiplet configurations Altug Koker, Eric Finley, Varghese George, Sanjeev Jahagirdar, Josh B. Mastronarde +6 more 2024-11-12
12112398 Disaggregation of system-on-chip (SOC) architecture Naveen Matam, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker +6 more 2024-10-08
12056789 Disaggregation of system-on-chip (SOC) architecture Naveen Matam, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker +6 more 2024-08-06
11763416 Disaggregation of system-on-chip (SOC) architecture Naveen Matam, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker +6 more 2023-09-19
11756150 Disaggregation of system-on-chip (SOC) architecture Naveen Matam, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker +6 more 2023-09-12
11410266 Disaggregation of System-On-Chip (SOC) architecture Naveen Matam, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker +6 more 2022-08-09
11386521 Enabling product SKUS based on chiplet configurations Altug Koker, Eric Finley, Varghese George, Sanjeev Jahagirdar, Josh B. Mastronarde +6 more 2022-07-12
10909652 Enabling product SKUs based on chiplet configurations Altug Koker, Eric Finley, Varghese George, Sanjeev Jahagirdar, Josh B. Mastronarde +6 more 2021-02-02
10803548 Disaggregation of SOC architecture Naveen Matam, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker +6 more 2020-10-13
7904701 Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache Anthony Babella, Allan Wong, Brian D. Rauchfuss 2011-03-08
7793187 Checking output from multiple execution units Allan Wong 2010-09-07
D592319 Textured architectural panel 2009-05-12