Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9115821 | Condensate valve | Heinz Bauer | 2015-08-25 |
| 6154084 | Method for switching voltages higher than a supply voltage on a semiconductor chip with a circuit configuration | — | 2000-11-28 |
| 6136717 | Method for producing a via hole to a doped region | Walter Neumueller | 2000-10-24 |
| 6034902 | Solid-state memory device | Thomas Zettler, Wolfgang Pockrandt, Georg Georgakos | 2000-03-07 |
| 5883832 | Electrically erasable and programmable non-volatile storage location | Georg Tempel | 1999-03-16 |
| 5846879 | Contact structure for vertical chip connections | Johann Alsmeier, Walter Neumuller | 1998-12-08 |
| 5798297 | Method for producing a semiconductor component with electrical connection terminals for high integration density | Johann Alsmeier | 1998-08-25 |
| 5148250 | Bipolar transistor as protective element for integrated circuits | Xaver Guggenmos | 1992-09-15 |
| 5126816 | Integrated circuit with anti latch-up circuit in complementary MOS circuit technology | Werner Reczek, Wolfgang Pribyl | 1992-06-30 |
| 5100811 | Integrated circuit containing bi-polar and complementary MOS transistors on a common substrate and method for the manufacture thereof | Franz Neppl | 1992-03-31 |
| 5045716 | Integrated circuit in complementary circuit technology comprising a substrate bias voltage generator | Dezso Takacs | 1991-09-03 |
| 5034338 | Circuit containing integrated bipolar and complementary MOS transistors on a common substrate | Franz Neppl | 1991-07-23 |
| 5013678 | Method of making an integrated circuit comprising load resistors arranged on the field oxide zones which separate the active transistor zones | Franz Neppl | 1991-05-07 |
| 4960489 | Method for self-aligned manufacture of contacts between interconnects contained in wiring levels arranged above one another in an integrated circuit | Guenther Roeska, Franz Neppl | 1990-10-02 |
| 4884117 | Circuit containing integrated bipolar and complementary MOS transistors on a common substrate | Franz Neppl | 1989-11-28 |
| 4873668 | Integrated circuit in complementary circuit technology comprising a substrate bias generator | Dezso Takacs | 1989-10-10 |
| 4855245 | Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate | Franz Neppl | 1989-08-08 |
| 4807010 | Integrated circuit in complementary circuit technology comprising a substrate bias voltage generator and a Schottky diode | Dezso Takacs | 1989-02-21 |
| 4798974 | Integrated circuit comprising a latch-up protection circuit in complementary MOS-circuitry technology | Werner Reczek | 1989-01-17 |
| 4791317 | Latch-up protection circuit for integrated circuits using complementary mos circuit technology | Werner Reczek | 1988-12-13 |
| 4791316 | Latch-up protection circuit for integrated circuits using complementary MOS circuit technology | Werner Reczek, Wolfgang Pribyl | 1988-12-13 |
| 4761384 | Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing | Franz Neppl, Erwin Jacobs, Carlos-Alberto Mazure-Espejo | 1988-08-02 |
| 4717686 | Method for the simultaneous manufacture of bipolar and complementary MOS transistors on a common silicon substrate | Erwin Jacobs | 1988-01-05 |