| 8086977 |
Design Structure for switching digital circuit clock net driver without losing clock pulses |
Jethro C. Law, Kirk E. Morrow, Glen A. Wiedemeier |
2011-12-27 |
| 7888968 |
Configurable pre-emphasis driver with selective constant and adjustable output impedance modes |
Daniel M. Dreps, Dhaval Sejpal |
2011-02-15 |
| 7821300 |
System and method for converting between CML signal logic families |
Dan P. Bernard, Glen A. Wiedemeier |
2010-10-26 |
| 7752480 |
System and method for switching digital circuit clock net driver without losing clock pulses |
Jethro C. Law, Kirk E. Morrow, Glen A. Wiedemeier |
2010-07-06 |
| 7477068 |
System for reducing cross-talk induced source synchronous bus clock jitter |
Bao G. Truong, Daniel M. Dreps, Anand Haridass, Joel D. Ziegelbein |
2009-01-13 |
| 7457091 |
Pulldown driver with gate protection for legacy interfaces |
Dan P. Bernard, Glen A. Wiedemeier |
2008-11-25 |
| 7382151 |
Method for reducing cross-talk induced source synchronous bus clock jitter |
Bao G. Truong, Daniel M. Dreps, Anand Haridass, Joel D. Ziegelbein |
2008-06-03 |
| 7212035 |
Logic line driver system for providing an optimal driver characteristic |
Daniel M. Dreps, Glen A. Wiedemeier, Joel D. Ziegelbein |
2007-05-01 |
| 7202723 |
Adjustable switchpoint receiver |
Daniel M. Dreps, Glen A. Wiedemeier |
2007-04-10 |
| 6906550 |
Modable dynamic terminator for high speed digital communications |
Daniel M. Dreps |
2005-06-14 |
