JM

Jaideep Mukherjee

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
📍 San Jose, CA: #12,320 of 32,062 inventorsTop 40%
🗺 California: #124,610 of 386,348 inventorsTop 35%
Overall (All Time): #1,176,951 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
10303828 Integrated circuit simulation with efficient memory usage Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen 2019-05-28
10248745 Integrated circuit simulation with variability analysis for efficient memory usage Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen 2019-04-02
10248747 Integrated circuit simulation with data persistency for efficient memory usage Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen 2019-04-02
9038008 System and method for containing analog verification IP Donald J. O'Riordan, Richard J. O'Donovan 2015-05-19