JD

James E. DeMaris

AD Analog Devices: 3 patents #564 of 1,943Top 30%
NS National Semiconductor: 2 patents #867 of 2,238Top 40%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Battle Ground, WA: #32 of 194 inventorsTop 20%
🗺 Washington: #16,830 of 76,902 inventorsTop 25%
Overall (All Time): #846,071 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
9772668 Power shutdown with isolation logic in I/O power domain Tobing Soebroto, Jose L. Medero, Scott J. Tucker 2017-09-26
7606092 Testing for SRAM memory data retention Michael D. Eby, Gregory P. Mikol 2009-10-20
6744659 Source-biased memory cell array Michael D. Eby, Gregory P. Mikol 2004-06-01
6618309 Adjustable memory self-timing circuit Michael D. Eby 2003-09-09
5136189 BiCMOS input circuit for detecting signals out of ECL range 1992-08-04
5103121 Input buffer regenerative latch for ECL levels Dennis L. Wendell, Jeffrey B. Chritz 1992-04-07