Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9772668 | Power shutdown with isolation logic in I/O power domain | James E. DeMaris, Jose L. Medero, Scott J. Tucker | 2017-09-26 |
| 8975919 | Dual row I/O with logic embedded between rows | — | 2015-03-10 |
| 8495531 | Method and system for providing an architecture for selecting and using components for an electronic design | Jeffrey K. Ng, Adam R. Traidman | 2013-07-23 |
| 7568177 | System and method for power gating of an integrated circuit | Ankur Gupta, Hendy Kosasih, Richard Chou | 2009-07-28 |