Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5393690 | Method of making semiconductor having improved interlevel conductor insulation | Al F. Tasch, Jr., Pallab K. Chatterjee | 1995-02-28 |
| 5202574 | Semiconductor having improved interlevel conductor insulation | Al F. Tasch, Jr., Pallab K. Chatterjee | 1993-04-13 |
| 4553316 | Self-aligned gate method for making MESFET semiconductor | Theodore W. Houston, Al F. Tasch, Jr., Henry M. Darley | 1985-11-19 |
| 4535528 | Method for improving reflow of phosphosilicate glass by arsenic implantation | Devereaux C. Chen | 1985-08-20 |
| 4455738 | Self-aligned gate method for making MESFET semiconductor | Theodore W. Houston, Al F. Tasch, Jr., Henry M. Darley | 1984-06-26 |
| 4384301 | High performance submicron metal-oxide-semiconductor field effect transistor device structure | Al F. Tasch, Jr., Pallab K. Chatterjee | 1983-05-17 |
| 4358340 | Submicron patterning without using submicron lithographic technique | — | 1982-11-09 |
| 4355454 | Coating device with As.sub.2 -O.sub.3 -SiO.sub.2 | Al F. Tasch, Jr. | 1982-10-26 |
| 4356040 | Semiconductor device having improved interlevel conductor insulation | Al F. Tasch, Jr., Pallab K. Chatterjee | 1982-10-26 |
| 4319260 | Multilevel interconnect system for high density silicon gate field effect transistors | Al F. Tasch, Jr. | 1982-03-09 |
| 4305200 | Method of forming self-registering source, drain, and gate contacts for FET transistor structures | John L. Moll, Juliana Manoliu | 1981-12-15 |
| 4203125 | Buried storage punch through dynamic ram cell | Pallab K. Chatterjee, Geoff W. Taylor, Al F. Tasch, Jr. | 1980-05-13 |