Issued Patents All Time
Showing 1–25 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12272399 | Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement | — | 2025-04-08 |
| 12198760 | Differential programming of two-terminal memory with intrinsic error suppression and wordline coupling | — | 2025-01-14 |
| 12154624 | Differential programming of two-terminal memory with program detection and multi-path disablement | — | 2024-11-26 |
| 12100449 | Differential programming of two-terminal resistive switching memory with intrinsic error suppression | — | 2024-09-24 |
| 12080347 | Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement | — | 2024-09-03 |
| 11973500 | Configuration bit using RRAM | Sang Thanh Nguyen, Cung Vu | 2024-04-30 |
| 11967376 | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip | Sung Hyun Jo, Sang Thanh Nguyen, Jeremy Guy, Zhi Li | 2024-04-23 |
| 11790999 | Resistive random access memory erase techniques and apparatus | Jeremy Guy, Sung Hyun Jo, Ruchirkumar D. Shah, Liang Zhao | 2023-10-17 |
| 11450384 | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip | Sung Hyun Jo, Sang Thanh Nguyen, Zhi Li | 2022-09-20 |
| 11437100 | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip | Sung Hyun Jo, Sang Thanh Nguyen, Zhi Li | 2022-09-06 |
| 11430517 | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip | Sung Hyun Jo, Sang Thanh Nguyen, Zhi Li | 2022-08-30 |
| 11430516 | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip | Sung Hyun Jo, Sang Thanh Nguyen, Jeremy Guy, Zhi Li | 2022-08-30 |
| 11423984 | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip | Sung Hyun Jo, Sang Thanh Nguyen, Zhi Li | 2022-08-23 |
| 11393529 | Capacitance measurement and apparatus for resistive switching memory devices | Cung Vu | 2022-07-19 |
| 11270769 | Network router device with hardware-implemented lookups including two-terminal non-volatile memory | Mehdi Asnaashari | 2022-03-08 |
| 11227654 | Resistive random-access memory and architecture with select and control transistors | — | 2022-01-18 |
| 11222696 | Computing memory architecture | Mehdi Asnaashari, Christophe Sucur, Sylvain Dubois | 2022-01-11 |
| 11127460 | Resistive random access memory matrix multiplication structures and methods | Mehdi Asnaashari, Christophe Sucur, Sylvain Dubois | 2021-09-21 |
| 10998064 | Resistive random access memory program and erase techniques and apparatus | Jeremy Guy, Sung Hyun Jo, Ruchirkumar D. Shah, Liang Zhao | 2021-05-04 |
| 10957410 | Methods and apparatus for facilitated program and erase of two-terminal memory devices | Sang Thanh Nguyen | 2021-03-23 |
| 10847579 | Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture | Harry Yue Gee | 2020-11-24 |
| 10796751 | State change detection for two-terminal memory | Sang Thanh Nguyen, Tianhong Yan | 2020-10-06 |
| 10699785 | Computing memory architecture | Mehdi Asnaashari, Christophe Sucur, Sylvain Dubois | 2020-06-30 |
| 10658033 | Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor | Sung Hyun Jo | 2020-05-19 |
| 10541025 | Switching block configuration bit comprising a non-volatile memory cell | Sung Hyun Jo | 2020-01-21 |