Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6668362 | Hierarchical verification for equivalence checking of designs | Lisa McIlwain, Slawomir PILARSKI | 2003-12-23 |
| 6247165 | System and process of extracting gate-level descriptions from simulation tables for formal verification | Peter Wohl | 2001-06-12 |