DL

Daniel J. Lussier

MC Maker Communications: 5 patents #1 of 4Top 25%
ML Mindspeed Technologies, Llc.: 5 patents #23 of 197Top 15%
CS Conexant Systems: 3 patents #123 of 657Top 20%
SB Stratus Technologies Bermuda: 2 patents #14 of 49Top 30%
Overall (All Time): #300,350 of 4,157,543Top 8%
16
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8312318 Systems and methods of high availability cluster environment failover protection Simon Graham 2012-11-13
8234521 Systems and methods for maintaining lock step operation Simon Graham, Timothy M. Wegner, Jeffrey S. Somers, Steven Haid, John W. Edwards 2012-07-31
RE42092 Integrated circuit that processes communication packets with a buffer management engine having a pointer cache Joseph B. Tompkins, Wilson P. Snyder, II 2011-02-01
7099328 Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task Duane E. Galbi, Joseph B. Tompkins, Bruce Burns 2006-08-29
7046686 Integrated circuit that processes communication packets with a buffer management engine having a pointer cache Joseph B. Tompkins, Wilson P. Snyder, II 2006-05-16
6888830 Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters Wilson Parkhurst SNYDER II, Joseph B. Tompkins 2005-05-03
6822959 Enhancing performance by pre-fetching and caching data directly in a communication processor's register set Duane E. Galbi, Wilson P. Snyder, II 2004-11-23
6804239 Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information Joseph B. Tompkins, Wilson Parkhurst SNYDER II 2004-10-12
6760337 Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels Wilson P. Snyder, II, Joseph B. Tompkins 2004-07-06
6754223 Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processor Joseph B. Tompkins, Wilson P. Snyder, II 2004-06-22
6359891 Asynchronous transfer mode cell processing system with scoreboard scheduling Paul V. Bergantino 2002-03-19
6128303 Asynchronous transfer mode cell processing system with scoreboard scheduling Paul V. Bergantino 2000-10-03
5860148 Asynchronous transfer mode cell processing system with cell buffer space gathering Paul V. Bergantino 1999-01-12
5794025 Method and device for performing modulo-based arithmetic operations in an asynchronous transfer mode cell processing system Paul V. Bergantino 1998-08-11
5748630 Asynchronous transfer mode cell processing system with load multiple instruction and memory write-back Paul V. Bergantino 1998-05-05
5748631 Asynchronous transfer mode cell processing system with multiple cell source multiplexing Paul V. Bergantino 1998-05-05