Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9843813 | Delayed chroma processing in block processing pipelines | Guy Cote | 2017-12-12 |
| 9691360 | Alpha channel power savings in graphics unit | Brijesh Tripathi, Nitin Bhargava | 2017-06-27 |
| 9571846 | Data storage and access in block processing pipelines | Timothy J. Millet, Mark P. Rygh, Jim C. Chou, Guy Cote, Gaurav S. Gulati +2 more | 2017-02-14 |
| 9473778 | Skip thresholding in pipelined video encoders | Jim C. Chou, Guy Cote | 2016-10-18 |
| 9299122 | Neighbor context processing in block processing pipelines | Guy Cote | 2016-03-29 |
| 9270999 | Delayed chroma processing in block processing pipelines | Guy Cote | 2016-02-23 |
| 9196187 | System and method of reducing power using a display inactive indication | Peter F. Holland | 2015-11-24 |
| 9191551 | Pixel normalization | Brijesh Tripathi, Nitin Bhargava | 2015-11-17 |
| 9123278 | Performing inline chroma downsampling with reduced power consumption | Brijesh Tripathi, Nitin Bhargava | 2015-09-01 |
| 8963946 | Non-real-time dither using a programmable matrix | Brijesh Tripathi, Wolfgang Roethig | 2015-02-24 |
| 8797359 | Inline image rotation | Brijesh Tripathi, Nitin Bhargava | 2014-08-05 |
| 8775777 | Techniques for sourcing immediate values from a VLIW | Tyson J. Bergland, Michael J. M. Toksvig, Justin Michael Mahan, Edward A. Hutchins | 2014-07-08 |
| 8687922 | Parallel scaler processing | Brijesh Tripathi, Nitin Bhargava | 2014-04-01 |
| 8599208 | Shared readable and writeable global values in a graphics processor unit pipeline | Tyson J. Bergland, Edward A. Hutchins, Michael J. M. Toksvig, Justin Michael Mahan | 2013-12-03 |
| 8314803 | Buffering deserialized pixel data in a graphics processor unit pipeline | Tyson J. Bergland, Edward A. Hutchins, Michael J. M. Toksvig, Justin Michael Mahan | 2012-11-20 |