CW

Christopher C. Wanner

CC Compaq Computer: 7 patents #150 of 1,604Top 10%
HE Hewlett Packard Enterprise: 6 patents #459 of 4,473Top 15%
HP HP: 2 patents #5,870 of 16,619Top 40%
Overall (All Time): #314,791 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11635798 Dynamic OCP adjustment 2023-04-25
11190002 Circuits to identify protection device failures Bradley Winick, Howard Leverenz 2021-11-30
10063011 Multiple pins of different lengths corresponding to different data signaling rates 2018-08-28
9779037 Establishing connectivity of modular nodes in a pre-boot environment 2017-10-03
9645337 Connector modules to optically connect to electronic devices Kevin B. Leigh, George D. Megason, David W. Sherrod 2017-05-09
9213157 Connector modules to optically connect to electronic devices Kevin B. Leigh, George D. Megason, David W. Sherrod 2015-12-15
7272732 Controlling power consumption of at least one computer system Keith Farkas, Gopalakrishnan Janakiraman, Robert Stets, Chandrakant Patel 2007-09-18
7020757 Providing an arrangement of memory devices to enable high-speed data access Michael Ruhovets 2006-03-28
6088517 Interfacing direct memory access devices to a non-ISA bus Jeffrey C. Stevens, Robert A. Lester, Dwight D. Riley, David J. Maguire, James R. Edwards 2000-07-11
5802318 Universal serial bus keyboard system David E. Murray, David R. Wooten, Jr., Randall L. Hess, Jeff W. Wolford 1998-09-01
5778199 Blocking address enable signal from a device on a bus Robert L. Woods 1998-07-07
5774680 Interfacing direct memory access devices to a non-ISA bus Jeffrey C. Stevens, Robert A. Lester, Dwight D. Riley, David J. Maguire, James R. Edwards 1998-06-30
5437042 Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system Paul R. Culley, John A. Landry, Dale J. Mayer, Guy E. McSwain 1995-07-25
5278803 Memory column address strobe buffer and synchronization and data latch interlock 1994-01-11
5214767 Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes Alan L. Goodrum, Paul R. Culley 1993-05-25