Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7375874 | Light modulator with integrated drive and control circuitry | Vlad Novotny, Bharat Sastri | 2008-05-20 |
| 7251249 | Integrated high speed switch router using a multiport architecture | Bhanu Nanduri | 2007-07-31 |
| 7075701 | Light modulator with integrated drive and control circuitry | Vlad Novotny, Bharat Sastri | 2006-07-11 |
| 7015885 | MEMS devices monolithically integrated with drive and control circuitry | Vlad Novotny, Bharat Sastri | 2006-03-21 |
| 6589834 | Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current | Ritu Shrivastava | 2003-07-08 |
| 6472267 | DRAM cell having storage capacitor contact self-aligned to bit lines and word lines | Ritu Shrivastava | 2002-10-29 |
| 6403448 | Semiconductor devices having cooperative mode option at assembly stage and method thereof | — | 2002-06-11 |
| 6392267 | Flash EPROM array with self-aligned source contacts and programmable sector erase architecture | Ritu Shrivastava | 2002-05-21 |
| 6373089 | DRAM cell having storage capacitor contact self-aligned to bit lines and word lines | Ritu Shrivastava | 2002-04-16 |
| 6317135 | Shared memory graphics accelerator system | — | 2001-11-13 |
| 6301629 | High speed/low speed interface with prediction cache | Bharat Sastri, Thomas Alexander | 2001-10-09 |
| 6292416 | Apparatus and method of reducing the pre-charge time of bit lines in a random access memory | Subramani Kengeri | 2001-09-18 |
| 6157587 | Data sense arrangement for random access memory | Vipul Patel | 2000-12-05 |
| 6137746 | High performance random access memory with multiple local I/O lines | Subramani Kengeri | 2000-10-24 |
| 6133602 | Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures | Ritu Shrivastava | 2000-10-17 |
| 6081279 | Shared memory graphics accelerator system | — | 2000-06-27 |
| 6025214 | Fusible link structure for semiconductor devices | Ajit K. Medhekar | 2000-02-15 |
| 6020237 | Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures | Ritu Shrivastava | 2000-02-01 |
| 5994730 | DRAM cell having storage capacitor contact self-aligned to bit lines and word lines | Ritu Shrivastava | 1999-11-30 |
| 5872742 | Staggered pipeline access scheme for synchronous random access memory | Subramani Kengeri, Darryl G. Walker, Kenneth A. Poteet | 1999-02-16 |
| 5831315 | Highly integrated low voltage SRAM array with low resistance Vss lines | Subramani Kengeri | 1998-11-03 |
| 5808959 | Staggered pipeline access scheme for synchronous random access memory | Subramani Kengeri, Darryl G. Walker, Kenneth A. Poteet | 1998-09-15 |
| 5781497 | Random access memory word line select circuit having rapid dynamic deselect | Vipul Patel | 1998-07-14 |
| 5767565 | Semiconductor devices having cooperative mode option at assembly stage and method thereof | — | 1998-06-16 |
| 5747868 | Laser fusible link structure for semiconductor devices | Ajit K. Medhekar | 1998-05-05 |