CL

Chooi Pei Lim

IN Intel: 19 patents #2,136 of 30,777Top 7%
Overall (All Time): #230,179 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12316328 Via configurable edge-combiner with duty cycle correction Eah Loon Alan Chuah, Eng Huat Lee, Marian Serban, Marian Cretu 2025-05-27
12026008 Techniques for clock signal transmission in integrated circuits and interposers Jeffrey Christopher Chromczak, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy +1 more 2024-07-02
11500412 Techniques for clock signal transmission in integrated circuits and interposers Jeffrey Christopher Chromczak, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy +1 more 2022-11-15
10530367 Clock synchronization in multi-die field programmable gate array devices Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh 2020-01-07
9577649 Methods and apparatus for reducing power in clock distribution networks Boon Pin Liong 2017-02-21
9430433 Multi-layer distributed network Keong Hong Oh, Yee Liang Tan, Siang Poh Loh 2016-08-30
9401281 Mask set for fabricating integrated circuits and method of fabricating integrated circuits Jordan Plofsky, Danny Biran, Francis Man-Chit Chow 2016-07-26
9236864 Stacked integrated circuit with redundancy in die-to-die interconnects Siang Poh Loh 2016-01-12
9225335 Clock signal networks for structured ASIC devices Joo Ming Too, Yew Fatt Kok, Kar Keng Chua 2015-12-29
8793547 3D built-in self-test scheme for 3D assembly defect detection Siang Poh Loh 2014-07-29
8786080 Systems including an I/O stack and methods for fabricating such systems Jordan Plofsky, Yee Liang Tan, Teik Tiong Toong 2014-07-22
8786308 Method and apparatus for providing signal routing control Siang Poh Loh, Yee Liang Tan, Kar Keng Chua 2014-07-22
8758961 Mask set for fabricating integrated circuits and method of fabricating integrated circuits Jordan Plofsky, Danny Biran, Francis Man-Chit Chow 2014-06-24
8683405 Multi-layer distributed network Keong Hong Oh, Yee Liang Tan, Siang Poh Lob 2014-03-25
8595658 Clock signal networks for structured ASIC devices Joo Ming Too, Yew Fatt Kok, Kar Keng Chua 2013-11-26
8166429 Multi-layer distributed network Keong Hong Oh, Yee Liang Tan, Siang Poh Loh 2012-04-24
7679397 Techniques for precision biasing output driver for a calibrated on-chip termination circuit Yew Fatt Kok, Kok Heng Choe 2010-03-16
7622952 Periphery clock signal distribution circuitry for structured ASIC devices Siang Poh Loh, Hong Ming Siew 2009-11-24
7404169 Clock signal networks for structured ASIC devices Joo Ming Too, Yew Fatt Kok, Kar Keng Chua 2008-07-22