Issued Patents All Time
Showing 25 most recent of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12212338 | Syndrome decoder circuit | Chi-Shun Lin, Ngatik Cheung | 2025-01-28 |
| 11901899 | Monotonic counter memory system | Chi-Shun Lin | 2024-02-13 |
| 11314588 | Memory device and multi physical cells error correction method thereof | Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung | 2022-04-26 |
| 11114180 | Non-volatile memory device | Chi-Shun Lin, Ngatik Cheung, Douk-Hyoun Ryu, Ming-Huei Shieh | 2021-09-07 |
| 11088711 | Memory apparatus and data accessing method thereof | Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung | 2021-08-10 |
| 11010245 | Memory storage apparatus with dynamic data repair mechanism and method of dynamic data repair thereof | Ming-Huei Shieh, Seow Fong Lim, Ngatik Cheung, Chi-Shun Lin | 2021-05-18 |
| 11003529 | Encoding method and memory storage apparatus using the same | Ming-Huei Shieh, Chi-Shun Lin, Ngatik Cheung | 2021-05-11 |
| 10956259 | Error correction code memory device and codeword accessing method thereof | Ming-Huei Shieh, Chi-Shun Lin | 2021-03-23 |
| 10853167 | Memory apparatus having hierarchical error correction code layer | Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung | 2020-12-01 |
| 10811092 | RRAM with plurality of 1TnR structures | Chi-Shun Lin, Douk-Hyoun Ryu, Ming-Huei Shieh, Seow Fong Lim | 2020-10-20 |
| 10783973 | Memory device having parameter adjusting mechanism and method of adjusting parameter by memory device | Chi-Shun Lin | 2020-09-22 |
| 10514980 | Encoding method and memory storage apparatus using the same | Ming-Huei Shieh, Seow Fong Lim, Ngatik Cheung, Chi-Shun Lin | 2019-12-24 |
| 10372535 | Encoding method and a memory storage apparatus using the same | Ming-Huei Shieh, Seow Fong Lim, Ngatik Cheung, Chi-Shun Lin | 2019-08-06 |
| 10348337 | Data read method and memory storage device using the same | Ming-Huei Shieh, Chi-Shun Lin | 2019-07-09 |
| 10236913 | Error checking and correcting decoder | Ngatik Cheung | 2019-03-19 |
| 9836349 | Methods and systems for detecting and correcting errors in nonvolatile memory | Ming-Huei Shieh, Chi-Shun Lin | 2017-12-05 |
| 9798481 | Memory system includes a memory controller coupled to a non-volatile memory array configured to provide special write operation to write data in the non-volatile memory array before a board mount operation is applied and provde a regular write operation after a board mount operation is applied | Ming-Huei Shieh, Chi-Shun Lin | 2017-10-24 |
| 9720771 | Methods and systems for nonvolatile memory data management | Ming-Huei Shieh, Chi-Shun Lin | 2017-08-01 |
| 9563505 | Methods and systems for nonvolatile memory data management | Ming-Huei Shieh, Chi-Shun Lin | 2017-02-07 |
| 8028211 | Look-ahead built-in self tests with temperature elevation of functional elements | Michael J. Miller | 2011-09-27 |
| 7941723 | Clock generator and method for providing reliable clock signal using array of MEMS resonators | Jimmy Lee | 2011-05-10 |
| 7921400 | Method for forming integrated circuit device using cell library with soft error resistant logic cells | Shih-Ked Lee | 2011-04-05 |
| 7877657 | Look-ahead built-in self tests | Michael J. Miller | 2011-01-25 |
| 7859876 | Method and apparatus for CAM with reduced cross-coupling interference | Chau-Chin Wu | 2010-12-28 |
| RE41351 | CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same | Chau-Chin Wu | 2010-05-25 |