CK

Chiyi Kao

LS Lsi: 3 patents #448 of 1,740Top 30%
Lsi Logic: 1 patents #1,146 of 1,957Top 60%
Overall (All Time): #1,229,081 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8552560 Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing Hemanshu Bhatt, Dilip Vijay, Jayanthi Pallinti, Sey-Shing Sun, Hong Ying 2013-10-08
8076779 Reduction of macro level stresses in copper/low-K wafers Sey-Shing Sun, Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Hong Ying +1 more 2011-12-13
7531442 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying +3 more 2009-05-12
7205673 Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying 2007-04-17