Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6911846 | Method and apparatus for a 1 of N signal | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Michael R. Seningen | 2005-06-28 |
| 6571378 | Method and apparatus for a N-NARY logic circuit using capacitance isolation | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Michael R. Seningen | 2003-05-27 |
| 6347327 | Method and apparatus for N-nary incrementor | James S. Blomgren | 2002-02-12 |
| 6334183 | Method and apparatus for handling partial register accesses | James S. Blomgren | 2001-12-25 |
| 6334136 | Dynamic 3-level partial result merge adder | James S. Blomgren | 2001-12-25 |
| 6324239 | Method and apparatus for a 1 of 4 shifter | Terence M. Potter, James S. Blomgren | 2001-11-27 |
| 6301600 | Method and apparatus for dynamic partitionable saturating adder/subtractor | James S. Blomgren | 2001-10-09 |
| 6301597 | Method and apparatus for saturation in an N-NARY adder/subtractor | James S. Blomgren | 2001-10-09 |
| 6288589 | Method and apparatus for generating clock signals | Terence M. Potter, James S. Blomgren, Stephen C. Horne | 2001-09-11 |
| 6275841 | 1-of-4 multiplier | Terence M. Potter, James S. Blomgren | 2001-08-14 |
| 6272514 | Method and apparatus for interruption of carry propagation on partition boundaries | James S. Blomgren | 2001-08-07 |
| 6268746 | Method and apparatus for logic synchronization | Terence M. Potter, James S. Blomgren, Stephen C. Horne | 2001-07-31 |
| 6269387 | Method and apparatus for 3-stage 32-bit adder/subtractor | James S. Blomgren | 2001-07-31 |
| 6252425 | Method and apparatus for an N-NARY logic circuit | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Michael R. Seningen | 2001-06-26 |
| 6233707 | Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock | Terence M. Potter, James S. Blomgren, Stephen C. Horne | 2001-05-15 |
| 6223199 | Method and apparatus for an N-NARY HPG gate | James S. Blomgren | 2001-04-24 |
| 6219687 | Method and apparatus for an N-nary Sum/HPG gate | James S. Blomgren | 2001-04-17 |
| 6219686 | Method and apparatus for an N-NARY sum/HPG adder/subtractor gate | James S. Blomgren | 2001-04-17 |
| 6216147 | Method and apparatus for an N-nary magnitude comparator | James S. Blomgren | 2001-04-10 |
| 6216146 | Method and apparatus for an N-nary adder gate | James S. Blomgren | 2001-04-10 |
| 6154120 | Method and apparatus for an N-nary equality comparator | James S. Blomgren | 2000-11-28 |
| 6124735 | Method and apparatus for a N-nary logic circuit using capacitance isolation | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Michael R. Seningen | 2000-09-26 |
| 6118304 | Method and apparatus for logic synchronization | Terence M. Potter, James S. Blomgren, Stephen C. Horne | 2000-09-12 |
| 6107835 | Method and apparatus for a logic circuit with constant power consumption | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Michael R. Seningen | 2000-08-22 |
| 6069497 | Method and apparatus for a N-nary logic circuit using 1 of N signals | James S. Blomgren, Terence M. Potter, Stephen C. Horne, Michael R. Seningen | 2000-05-30 |