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Diminution of test templates in test suites |
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| 10026500 |
Address translation stimuli generation for post-silicon functional validation |
Shai Doron |
2018-07-17 |
| 9633155 |
Circuit modification |
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| 8938646 |
Mutations on input for test generation |
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2015-01-20 |
| 8892386 |
Method and apparatus for post-silicon testing |
Allon Adir, Eyal Bin, Shady Copty, Shimon Landa, Amir Nahir +2 more |
2014-11-18 |
| 8601418 |
Instruction-by-instruction checking on acceleration platforms |
Debapriya Chatterjee, Ronny Morad, Avi Ziv |
2013-12-03 |
| 8589892 |
Verification of speculative execution |
Laurent Fournier, Michal Rimon |
2013-11-19 |
| 8245164 |
Method of verification of address translation mechanisms |
Yoav Katz, Elena Tsanko |
2012-08-14 |
| 7370296 |
Modeling language and method for address translation design mechanisms in test generation |
Allon Adir, Roy Emek, Yoav Katz, Michael Vinov |
2008-05-06 |
| 7028067 |
Generation of mask-constrained floating-point addition and subtraction test cases, and method and system therefor |
Ziv Abraham, Sigal Asaf, Shay Zadok |
2006-04-11 |
