Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7411968 | Two-dimensional queuing/de-queuing methods and systems for implementing the same | Simon Chong, Man Dieu Trinh | 2008-08-12 |
| 7295564 | Virtual output queue (VoQ) management method and apparatus | Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi | 2007-11-13 |
| 7154853 | Rate policing algorithm for packet flows | Jean-Michel Caia, Jing Ling, Juan-Carlos Calderon, Vivek Joshi | 2006-12-26 |
| 7065628 | Increasing memory access efficiency for packet applications | Juan-Carlos Calderon, Jing Ling, Jean-Michel Caia, Vivek Joshi | 2006-06-20 |
| 7061867 | Rate-based scheduling for packet applications | Jing Ling, Jean-Michel Caia, Juan-Carlos Calderon, Vivek Joshi | 2006-06-13 |
| 6944728 | Interleaving memory access | Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Jing Ling | 2005-09-13 |
| 6892284 | Dynamic memory allocation for assigning partitions to a logical port from two groups of un-assigned partitions based on two threshold values | Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Steve John Clohset | 2005-05-10 |
| 6724767 | Two-dimensional queuing/de-queuing methods and systems for implementing the same | Simon Chong, Man Dieu Trinh | 2004-04-20 |
| 6603768 | Multi-protocol conversion assistance method and system for a network accelerator | Ryszard Bleszynski, Simon Chong, David Anthony Stelliga | 2003-08-05 |
| 6501731 | CBR/VBR traffic scheduler | Simon Chong, Ryszard Bleszynski, David Anthony Stelliga | 2002-12-31 |
| 6311212 | Systems and methods for on-chip storage of virtual connection descriptors | Simon Chong, David Anthony Stelliga, Ryszard Bleszynski, Man Dieu Trinh | 2001-10-30 |