Issued Patents All Time
Showing 25 most recent of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12316731 | Device with low-power synchronizing circuitry and related method | Namerita Khanna, Rajnish Garg, Rohit Gupta | 2025-05-27 |
| 12210373 | Low overhead mesochronous digital interface | Sharad Gupta, Anupam Jain | 2025-01-28 |
| 12093193 | High throughput digital filter architecture for processing unary coded data | Rupesh SINGH | 2024-09-17 |
| 12088326 | Sigma-delta analog-to-digital converter circuit with data sharing for power saving | Abhishek Jain | 2024-09-10 |
| 12086568 | High throughput parallel architecture for recursive sinusoid synthesizer | Rupesh SINGH | 2024-09-10 |
| 12055989 | Clock delay circuit for chip reset architecture | Vikas Chelani | 2024-08-06 |
| 12009830 | Timing skew mismatch calibration for time interleaved analog to digital converters | Vikram Singh | 2024-06-11 |
| 11989148 | Data bridge for interfacing source synchronous datapaths with unknown clock phases | Rupesh SINGH | 2024-05-21 |
| 11979167 | Low power and high speed data weighted averaging (DWA) to binary converter circuit | Sharad Gupta | 2024-05-07 |
| 11933861 | Phase-independent testing of a converter | Sharad Gupta | 2024-03-19 |
| 11921537 | Method and circuit for calibration of high-speed data interface | Jeet Narayan Tiwari | 2024-03-05 |
| 11909410 | Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error | Sharad Gupta | 2024-02-20 |
| 11901919 | On chip test architecture for continuous time delta sigma analog-to-digital converter | Abhishek Jain, Sharad Gupta | 2024-02-13 |
| 11689191 | High frequency resolution digital sinusoid generator | — | 2023-06-27 |
| 11656848 | High throughput parallel architecture for recursive sinusoid synthesizer | Rupesh SINGH | 2023-05-23 |
| 11563443 | High speed data weighted averaging (DWA) to binary converter circuit | Rupesh SINGH | 2023-01-24 |
| 11552646 | Timing skew mismatch calibration for time interleaved analog to digital converters | Vikram Singh | 2023-01-10 |
| 11522553 | Sigma-delta analog-to-digital converter circuit with real time correction for digital-to-analog converter mismatch error | Sharad Gupta | 2022-12-06 |
| 11463098 | Method and device for testing successive approximation register analog-to-digital converters | Sri Ram Gupta, Rupesh SINGH | 2022-10-04 |
| 11417371 | First order memory-less dynamic element matching technique | Rupesh SINGH, Vivek Tripathi | 2022-08-16 |
| 11411565 | Clock and data recovery circuit | Rupesh SINGH | 2022-08-09 |
| 11336194 | DC-AC converter | Vikram Singh, Vineet Mehta, Jitender Singh | 2022-05-17 |
| 11177799 | Debounce circuit with noise immunity and glitch event tracking | Vikas Chelani | 2021-11-16 |
| 11094354 | First order memory-less dynamic element matching technique | Rupesh SINGH, Vivek Tripathi | 2021-08-17 |
| 11092993 | Digital sinusoid generator | Rupesh SINGH | 2021-08-17 |