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Method and system for recovery of metals from spent lithium ion batteries |
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High throughput digital filter architecture for processing unary coded data |
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High throughput parallel architecture for recursive sinusoid synthesizer |
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Data bridge for interfacing source synchronous datapaths with unknown clock phases |
Ankur Bal |
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| 11656848 |
High throughput parallel architecture for recursive sinusoid synthesizer |
Ankur Bal |
2023-05-23 |
| 11563443 |
High speed data weighted averaging (DWA) to binary converter circuit |
Ankur Bal |
2023-01-24 |
| 11463098 |
Method and device for testing successive approximation register analog-to-digital converters |
Ankur Bal, Sri Ram Gupta |
2022-10-04 |
| 11417371 |
First order memory-less dynamic element matching technique |
Ankur Bal, Vivek Tripathi |
2022-08-16 |
| 11411565 |
Clock and data recovery circuit |
Ankur Bal |
2022-08-09 |
| 11092993 |
Digital sinusoid generator |
Ankur Bal |
2021-08-17 |
| 11094354 |
First order memory-less dynamic element matching technique |
Ankur Bal, Vivek Tripathi |
2021-08-17 |
| 11043960 |
Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter |
Ankur Bal |
2021-06-22 |
| 10862503 |
Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator |
Ankur Bal |
2020-12-08 |
| 10484165 |
Latency buffer circuit with adaptable time shift |
Ankur Bal |
2019-11-19 |
| 10218380 |
High speed data weighted averaging architecture |
Ankur Bal |
2019-02-26 |
| 10211850 |
High speed data weighted averaging architecture |
Ankur Bal |
2019-02-19 |
| 10050640 |
High speed data weighted averaging architecture |
Ankur Bal |
2018-08-14 |