Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182046 | Data burst suspend mode using pause detection | Eric N. Lee, Leonid Minz, Yoav Weinberg, Luigi Pilolli | 2024-12-31 |
| 12111781 | Data burst suspend mode using multi-level signaling | Eric N. Lee, Leonid Minz, Yoav Weinberg, Luigi Pilolli | 2024-10-08 |
| 11848071 | Systems and methods involving write training to improve data valid windows | Agatino Massimo Maccarrone, Luigi Pilolli, Chin-Yu Chen | 2023-12-19 |
| 11733887 | Write training in memory devices by adjusting delays based on data patterns | Luigi Pilolli, Guan Wang, Qiang Tang | 2023-08-22 |
| 11544208 | Wave pipeline including synchronous stage | Kaveh Shakeri | 2023-01-03 |
| 11528015 | Level shifter with reduced duty cycle variation | Luigi Pilolli, Myung-Gyoo Won | 2022-12-13 |
| 11367473 | Wave pipeline | Kaveh Shakeri, Qiang Tang, Eric N. Lee | 2022-06-21 |
| 11211104 | Systems and methods involving write training to improve data valid windows | Agatino Massimo Maccarrone, Luigi Pilolli, Chin-Yu Chen | 2021-12-28 |
| 11079946 | Write training in memory devices | Luigi Pilolli, Guan Wang, Qiang Tang | 2021-08-03 |
| 11061836 | Wave pipeline including synchronous stage | Kaveh Shakeri | 2021-07-13 |
| 10911033 | Level shifter with reduced duty cycle variation | Luigi Pilolli, Myung-Gyoo Won | 2021-02-02 |
| 10891993 | Wave pipeline | Kaveh Shakeri, Qiang Tang, Eric N. Lee | 2021-01-12 |
| 10861517 | Systems and methods involving memory-side (NAND-side) write training to improve data valid windows | Agatino Massimo Maccarrone, Luigi Pilolli, Chin-Yu Chen | 2020-12-08 |
| 10802721 | Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal | Eric N. Lee, Qiang Tang, Hoon Choi, Daesik Song | 2020-10-13 |
| 10714160 | Wave pipeline | Kaveh Shakeri | 2020-07-14 |
| 10387048 | Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal | Eric N. Lee, Qiang Tang, Hoon Choi, Daesik Song | 2019-08-20 |
| 10019170 | Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal | Eric N. Lee, Qiang Tang, Hoon Choi, Daesik Song | 2018-07-10 |
| 9460803 | Data path with clock-data tracking | Qiang Tang, Hoon Choi, Eric N. Lee, Ramin Ghodsi | 2016-10-04 |