Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6985380 | SRAM with forward body biasing to improve read cell stability | Muhammad M. Khellah, Dinesh Somasekhar, Ali R. Farhang, Gunjan H. Pandya, Vivek K. De | 2006-01-10 |
| 6952376 | Method and apparatus to generate a reference value in a memory array | Dinesh Somasekhar, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi +2 more | 2005-10-04 |
| 6909652 | SRAM bit-line reduction | Dinesh Somasekhar, Muhammad M. Khellah, Vivek K. De | 2005-06-21 |
| 6906973 | Bit-line droop reduction | Dinesh Somasekhar, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi +2 more | 2005-06-14 |
| 6903984 | Floating-body DRAM using write word line for increased retention time | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah +1 more | 2005-06-07 |
| 6879531 | Reduced read delay for single-ended sensing | Dinesh Somasekhar, Fatih Hamzaoglu, Vivek K. De | 2005-04-12 |
| 6876571 | Static random access memory having leakage reduction circuit | Muhammad M. Khellah, Dinesh Somasekhar, Vivek K. De | 2005-04-05 |
| 6831871 | Stable memory cell read | Muhammad M. Khellah, Dinesh Somasekhar, Vivek K. De | 2004-12-14 |
| 6801463 | Method and apparatus for leakage compensation with full Vcc pre-charge | Muhammad M. Khellah, Dinesh Somasekhar, Vivek K. De | 2004-10-05 |
| 6801465 | Apparatus and method for a memory storage cell leakage cancellation scheme | Dinesh Somasekhar, Fatih Hamzaoglu, Vivek K. De | 2004-10-05 |
| 6784688 | Skewed repeater bus | Muhammad M. Khellah, James W. Tschanz, Vivek K. De | 2004-08-31 |
| 6744301 | System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise | James W. Tschanz, Siva G. Narendra, Vivek K. De | 2004-06-01 |
| 6724648 | SRAM array with dynamic voltage for reducing active leakage power | Muhammad M. Khellah, Vivek K. De, Dinesh Somasekhar | 2004-04-20 |
| 6724649 | Memory cell leakage reduction | Dinesh Somasekhar, Vivek K. De | 2004-04-20 |
| 6683467 | Method and apparatus for providing rotational burn-in stress testing | Ali Keshavarzi, David M. Wu, Vivek K. De | 2004-01-27 |
| 6653866 | Domino logic with output predischarge | Siva G. Narendra, Vivek K. De | 2003-11-25 |
| 6608786 | Apparatus and method for a memory storage cell leakage cancellation scheme | Dinesh Somasekhar, Fatih Hamzaoglu, Vivek K. De | 2003-08-19 |
| 6529045 | NMOS precharge domino logic | Reed D. Spotten, Vivek K. De | 2003-03-04 |
| 6519176 | Dual threshold SRAM cell for single-ended sensing | Fatih Hamzaoglu, Ali Keshavarzi, Siva G. Narendra, Vivek K. De | 2003-02-11 |
| 6515513 | Reducing leakage currents in integrated circuits | James W. Tschanz, Vivek K. De | 2003-02-04 |
| 6509772 | Flip-flop circuit with transmission-gate sampling | Zhanping Chen | 2003-01-21 |
| 6496040 | Trading off gate delay versus leakage current using device stack effect | Siva G. Narendra, Vivek K. De | 2002-12-17 |
| 6492837 | Domino logic with output predischarge | Siva G. Narendra, Vivek K. De | 2002-12-10 |
| 6486706 | Domino logic with low-threshold NMOS pull-up | Siva G. Narendra, Vivek K. De | 2002-11-26 |
| 6400206 | Dual-level voltage shifters for low leakage power | Hyungwon Kim | 2002-06-04 |