Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10152820 | Texture address mode discarding filter taps | Robert M. Toth | 2018-12-11 |
| 9870640 | Techniques and architecture for improved vertex processing | Rahul P. Sathe | 2018-01-16 |
| 9449419 | Post tessellation edge cache | Rahul P. Sathe, Karthik Vaidyanathan | 2016-09-20 |
| 9449420 | Reducing the domain shader/tessellator invocations | Rahul P. Sathe | 2016-09-20 |
| 9208602 | Techniques and architecture for improved vertex processing | Rahul P. Sathe | 2015-12-08 |