Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10573375 | Methods and circuitry for programming non-volatile resistive switches using varistors | Yue-Song He, Rusli Kurniawan, Christopher J. Pass, Andy L. Lee, Jeffrey T. Watt +2 more | 2020-02-25 |
| 10447275 | Integrated circuits with programmable non-volatile resistive switch elements | Andy L. Lee, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He | 2019-10-15 |
| 10269426 | Integrated circuits with complementary non-volatile resistive memory elements | Rusli Kurniawan, Yue-Song He, Andy L. Lee, Jeffrey T. Watt, Christopher J. Pass | 2019-04-23 |
| 10090840 | Integrated circuits with programmable non-volatile resistive switch elements | Andy L. Lee, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He | 2018-10-02 |
| 8716876 | Systems and methods for stacking a memory chip above an integrated circuit chip | Jon M. Long | 2014-05-06 |
| 8492798 | Electrical fuse with sacrificial contact | Shih-Lin Lee, Peter J. McElheny, Christopher J. Pass | 2013-07-23 |
| 8130538 | Non-volatile memory circuit including voltage divider with phase change memory devices | Peter J. McElheny, John C. Costello | 2012-03-06 |
| 7759226 | Electrical fuse with sacrificial contact | Shih-Lin Lee, Peter J. McElheny, Christopher J. Pass | 2010-07-20 |
| 7236398 | Structure of a split-gate memory cell | Myron W. Wong | 2007-06-26 |
| 6624467 | EEPROM active area castling | Peter J. McElheny, Raminda Udaya Madurawe, Minchang Liang | 2003-09-23 |
| 6472272 | Castled active area mask | Peter J. McElheny, Raminda Udaya Madurawe, Minchang Liang | 2002-10-29 |
| 6365929 | Scalable tunnel oxide window with no isolation edges | — | 2002-04-02 |
| 6265746 | Highly resistive interconnects | Raminda Udaya Madurawe, Charu Sardana, Peter J. McElheny | 2001-07-24 |
| 6187634 | Process for making an EEPROM active area castling | Peter J. McElheny, Raminda Udaya Madurawe, Minchang Liang | 2001-02-13 |
| 6127217 | Method of forming highly resistive interconnects | Raminda Udaya Madurawe, Charu Sardana, Peter J. McElheny | 2000-10-03 |
| 5905675 | Biasing scheme for reducing stress and improving reliability in EEPROM cells | Raminda Udaya Madurawe, Minchang Liang, James D. Sansbury, John E. Turner, John C. Costello +1 more | 1999-05-18 |
| 5904524 | Method of making scalable tunnel oxide window with no isolation edges | — | 1999-05-18 |