Issued Patents All Time
Showing 51–75 of 161 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8838946 | Packing lower half bits of signed data elements in two source registers in a destination register with saturation | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2014-09-16 |
| 8793475 | Method and apparatus for unpacking and moving packed data | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2014-07-29 |
| 8793299 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi +1 more | 2014-07-29 |
| 8745119 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi +1 more | 2014-06-03 |
| 8725787 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi +1 more | 2014-05-13 |
| 8639914 | Packing signed word elements from two source registers to saturated signed byte elements in destination register | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2014-01-28 |
| 8627053 | Method and apparatus for secure execution using a secure memory partition | — | 2014-01-07 |
| 8601246 | Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2013-12-03 |
| 8572140 | Deterministic lookup using hashed key in a multi-stride compressed trie structure | — | 2013-10-29 |
| 8565388 | Method and apparatus for data channel augmented auto attended voice response systems | — | 2013-10-22 |
| 8554938 | Web browser proxy-client video system and method | — | 2013-10-08 |
| 8549275 | Method and apparatus for secure execution using a secure memory partition | — | 2013-10-01 |
| 8521994 | Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2013-08-27 |
| 8499012 | System and method for attached storage stacking | — | 2013-07-30 |
| 8495346 | Processor executing pack and unpack instructions | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2013-07-23 |
| 8495123 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi +1 more | 2013-07-23 |
| 8488618 | Dual-connect service box with router bypass | Robert Fanfelle | 2013-07-16 |
| 8396915 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi +1 more | 2013-03-12 |
| 8356020 | Multi-level compressed look-up tables formed by logical operations to compress selected index bits | — | 2013-01-15 |
| 8347072 | Method and apparatus for secure execution using a secure memory partition | — | 2013-01-01 |
| 8190867 | Packing two packed signed data in registers with saturation | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2012-05-29 |
| 8185571 | Processor for performing multiply-add operations on packed data | Alexander Peleg, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi +1 more | 2012-05-22 |
| 7966482 | Interleaving saturated lower half of data elements from two source registers of packed data | Alexander Peleg, Yaakov Yaari, Larry M. Mennemeier, Benny Eitan | 2011-06-21 |
| 7921088 | Logical operations encoded by a function table for compressing index bits in multi-level compressed look-up tables | — | 2011-04-05 |
| 7908464 | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests | Mehul Kharidia, Tarun Kumar Tripathy, J. Sukarno Mertoguno | 2011-03-15 |