Issued Patents All Time
Showing 101–125 of 263 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9684488 | Combined adder and pre-adder for high-radix multiplier circuit | — | 2017-06-20 |
| 9619207 | Circuitry and methods for implementing Galois-field reduction | — | 2017-04-11 |
| 9613232 | Digital signal processing blocks with embedded arithmetic circuits | — | 2017-04-04 |
| 9606608 | Low power optimizations for a floating point multiplier | — | 2017-03-28 |
| 9600278 | Programmable device using fixed and configurable logic to implement recursive trees | — | 2017-03-21 |
| 9594928 | Multi-channel, multi-lane encryption circuitry and methods | — | 2017-03-14 |
| 9583218 | Configurable register circuitry for error detection and recovery | Michael D. Hutton | 2017-02-28 |
| 9582686 | Unique secure serial ID | Juju Joyce | 2017-02-28 |
| 9575725 | Specialized processing block with embedded pipelined accumulator circuitry | — | 2017-02-21 |
| 9552189 | Embedded floating-point operator circuitry | Bogdan Pasca | 2017-01-24 |
| 9553591 | Hybrid architecture for signal processing | Steven Perry, Richard Maiden | 2017-01-24 |
| 9552190 | Fused floating point datapath with correct rounding | Bogdan Pasca | 2017-01-24 |
| 9519807 | Hash generation circuitry and methods for multi-channel, multi-lane encryption and authentication | — | 2016-12-13 |
| 9507565 | Programmable device implementing fixed and floating point functionality in a mixed architecture | Keone Streicher, Yi-Wen Lin, Hyun Yi | 2016-11-29 |
| 9395953 | Large multiplier for programmable logic device | Kumara Tharmalingam | 2016-07-19 |
| 9391781 | Systems and methods for intermediate message authentication in a switched-path network | Shawn David Nicholl, Wally Haas | 2016-07-12 |
| 9379687 | Pipelined systolic finite impulse response filter | Volker Mauer | 2016-06-28 |
| 9348795 | Programmable device using fixed and configurable logic to implement floating-point rounding | — | 2016-05-24 |
| 9348557 | Fused floating point datapath with correct rounding | Bogdan Pasca | 2016-05-24 |
| 9344113 | Lempel Ziv compression architecture | — | 2016-05-17 |
| 9337844 | Generalized parallel counter structures in logic devices | — | 2016-05-10 |
| 9331714 | Circuit structure and method for high-speed forward error correction | Haiyun Yang, Peng Li, Divya Vijayaraghavan | 2016-05-03 |
| 9235540 | Flexible high speed forward error correction (FEC) physical medium attachment (PMA) and physical coding sublayer (PCS) connection system | Haiyun Yang, Peng Li | 2016-01-12 |
| 9207908 | Digital signal processing blocks with embedded arithmetic circuits | — | 2015-12-08 |
| 9208357 | FPGA configuration bitstream protection using multiple keys | Juju Joyce, Keone Streicher, David Jefferson, Srinivas T. Reddy, Nitin Prasad | 2015-12-08 |