Issued Patents All Time
Showing 26–50 of 263 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11301611 | Deterministic clustering and packing method for random logic on programmable integrated circuits | Gregg William Baeckler | 2022-04-12 |
| 11301213 | Reduced latency multiplier circuitry for very large numbers | Bogdan Pasca | 2022-04-12 |
| 11294626 | Floating-point dynamic range expansion | Bogdan Pasca | 2022-04-05 |
| 11275998 | Circuitry for low-precision deep learning | Sudarshan Srinivasan, Gregg William Baeckler, Duncan Moss, Sasikanth Avancha, Dipankar Das | 2022-03-15 |
| 11256978 | Hyperbolic functions for machine learning acceleration | Bogdan Pasca | 2022-02-22 |
| 11249726 | Integrated circuits with modular multiplication circuitry | Bogdan Pasca | 2022-02-15 |
| 11216532 | Circuitry for high-bandwidth, low-latency machine learning | Andrei-Mihai Hagiescu-Miriste | 2022-01-04 |
| 11216249 | Method and apparatus for performing field programmable gate array packing with continuous carry chains | Gregg William Baeckler | 2022-01-04 |
| 11210063 | Machine learning training architecture for programmable devices | Bogdan Pasca, Sergey Gribok, Gregg William Baeckler, Andrei Hagiescu | 2021-12-28 |
| 11175892 | Integrated circuits with machine learning extensions | Dongdong Chen | 2021-11-16 |
| 11163530 | Programmable-logic-directed multiplier mapping | Gregg William Baeckler | 2021-11-02 |
| 11137983 | Programmable device implementing fixed and floating point functionality in a mixed architecture | Keone Streicher, Yi-Wen Lin, Hyun Yi | 2021-10-05 |
| 11101925 | Decomposable forward error correction | Peng Li, Masashi Shimanouchi | 2021-08-24 |
| 11080019 | Method and apparatus for performing synthesis for field programmable gate array embedded feature placement | Gregg William Baeckler, Sergey Gribok | 2021-08-03 |
| 11016733 | Continuous carry-chain packing | Sergey Gribok, Gregg William Baeckler | 2021-05-25 |
| 11010134 | High radix subset code multiplier architecture | Gregg William Baeckler | 2021-05-18 |
| 11010131 | Floating-point adder circuitry with subnormal support | Bogdan Pasca | 2021-05-18 |
| 11003446 | Reduction operation mapping systems and methods | Gregg William Baeckler, Bogdan Pasca | 2021-05-11 |
| 10996926 | Variable precision floating-point multiplier | — | 2021-05-04 |
| 10970409 | Security RAM block with multiple partitions | — | 2021-04-06 |
| 10970042 | Integrated circuits with machine learning extensions | Dongdong Chen, Kevin A. Hurd | 2021-04-06 |
| 10942706 | Implementation of floating-point trigonometric functions in an integrated circuit device | Bogdan Pasca | 2021-03-09 |
| 10922471 | High performance regularized network-on-chip architecture | Gregg William Baeckler, Sergey Gribok | 2021-02-16 |
| 10871946 | Methods for using a multiplier to support multiple sub-multiplication operations | Gregg William Baeckler, Sergey Gribok, Dmitry N. Denisenko, Bogdan Pasca | 2020-12-22 |
| 10872130 | High performance QR decomposition systems and methods | — | 2020-12-22 |