Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7000041 | Method and an apparatus to efficiently handle read completions that satisfy a read request | Sridhar Muthrasanalluar | 2006-02-14 |
| 6978351 | Method and system to improve prefetching operations | Randy B. Osborne, Joseph A. Bennett, Jasmin Ajanovic | 2005-12-20 |
| 6976129 | Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture | Manoj Khare, Lily P. Looi, Akhilesh Kumar | 2005-12-13 |
| 6976115 | Peer-to-peer bus segment bridging | Jasmin Ajanovic, Joseph A. Bennett | 2005-12-13 |
| 6915365 | Mechanism for PCI I/O-initiated configuration cycles | Doug Moran, Vasudevan Shanmugasundaram | 2005-07-05 |
| 6859864 | Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line | Manoj Khare, Lily P. Looi, Akhilesh Kumar | 2005-02-22 |
| 6801976 | Mechanism for preserving producer-consumer ordering across an unordered interface | Bradford B. Congdon, Tony S. Rand, Deepak Ramachandran | 2004-10-05 |
| 6694383 | Handling service requests | Thai Nguyen, Robert J. Miller | 2004-02-17 |
| 6681292 | Distributed read and write caching implementation for optimized input/output applications | Mike Bell, Robert T. George, Bradford B. Congdon, Robert G. Blankenship, Duane January | 2004-01-20 |
| 6216247 | 32-bit mode for a 64-bit ECC capable memory subsystem | Elliot Garbus | 2001-04-10 |
| 6088762 | Power failure mode for a memory controller | — | 2000-07-11 |
| 5742831 | Methods and apparatus for maintaining cache coherency during copendency of load and store operations | — | 1998-04-21 |