Jay J. Sturges — 14 Patents at Intel

Jay J. Sturges has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 1994 and the most recent in April 2008. Jay J. Sturges ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Jay J. Sturges in Folsom, CA, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
7356809	Programmable interpretive virtual machine	—	2008-04-08	$22,423,000
6222564	Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controller	—	2001-04-24	$172,753,000
6138273	Programmable interpretive virtual machine	—	2000-10-24	$347,431,000
5930827	Method and apparatus for dynamic memory management by association of free memory blocks using a binary tree organized in an address and size dependent manner	—	1999-07-27	$181,024,000
5854637	Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controller	—	1998-12-29	$153,372,000
5761537	Method and apparatus for integrating three dimensional sound into a computer system having a stereo audio circuit	David I. Poisner	1998-06-02	$54,938,000
5742793	Method and apparatus for dynamic memory management by association of free memory blocks using a binary tree organized in an address and size dependent manner	Greg Hibdon	1998-04-21	$94,071,000
5572198	Method and apparatus for routing in reduced switch matrices to provide one hundred percent coverage	—	1996-11-05	$57,895,000
5530439	Deterministic method and an apparatus for minimal switch circuits	Randy C. Steele, Gregory B. Hibdon, Richard P. Vireday	1996-06-25	$66,281,000
5491666	Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof	—	1996-02-13	$132,405,000
5490266	Process oriented logic simulation having stability checking	—	1996-02-06	$40,865,000
5448525	Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof	—	1995-09-05	$57,710,000
5371495	Deterministic routing method for minimal switch circuits	Richard P. Vireday	1994-12-06	$56,548,000
5333139	Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain	—	1994-07-26	$21,513,000

Jay J. Sturges — 14 Patents

Issued Patents All Time

Patent Widget