| 7903552 |
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2011-03-08 |
| 7808989 |
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| 7733770 |
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2010-06-08 |
| 7457245 |
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2008-11-25 |
| 7310319 |
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| 7305493 |
Embedded transport acceleration architecture |
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| 7000048 |
Apparatus and method for parallel processing of network data on a single processing thread |
Dave B. Minturn |
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| 6647423 |
Direct message transfer between distributed processes |
Gregory J. Regnier, David S. Dunning, Donald F. Cameron |
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| 6167491 |
High performance digital electronic system architecture and memory circuit therefor |
— |
2000-12-26 |
| 6070219 |
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| 6011798 |
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— |
2000-01-04 |
| 5802580 |
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— |
1998-09-01 |
| 4837785 |
Data transfer system and method of operation thereof |
— |
1989-06-06 |
| 4800535 |
Interleaved memory addressing system and method using a parity signal |
— |
1989-01-24 |