Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7903552 | Directional and priority based flow control mechanism between nodes | Tanmay Gupta, Manoj Wadekar | 2011-03-08 |
| 7808989 | Multiple-domain processing system using hierarchically orthogonal switching fabric | Oleg Awsienko, Edward Butler, David B. Minturn, Joseph A. Schaefer, Gary Solomon | 2010-10-05 |
| 7733770 | Congestion control in a network | Tanmay Gupta, Manoj Wadekar | 2010-06-08 |
| 7457245 | Directional and priority based flow control mechanism between nodes | Tanmay Gupta, Manoj Wadekar | 2008-11-25 |
| 7310319 | Multiple-domain processing system using hierarchically orthogonal switching fabric | Oleg Awsienko, Edward Butler, David B. Minturn, Joseph A. Schaefer, Gary Solomon | 2007-12-18 |
| 7305493 | Embedded transport acceleration architecture | David B. Minturn, Hemal Shah, Annie Foong, Greg Regnier, Vikram Saletore | 2007-12-04 |
| 7000048 | Apparatus and method for parallel processing of network data on a single processing thread | Dave B. Minturn | 2006-02-14 |
| 6647423 | Direct message transfer between distributed processes | Gregory J. Regnier, David S. Dunning, Donald F. Cameron | 2003-11-11 |
| 6167491 | High performance digital electronic system architecture and memory circuit therefor | — | 2000-12-26 |
| 6070219 | Hierarchical interrupt structure for event notification on multi-virtual circuit network interface controller | Greg Regnier | 2000-05-30 |
| 6011798 | Adaptive transmit rate control scheduler | — | 2000-01-04 |
| 5802580 | High performance digital electronic system architecture and memory circuit thereof | — | 1998-09-01 |
| 4837785 | Data transfer system and method of operation thereof | — | 1989-06-06 |
| 4800535 | Interleaved memory addressing system and method using a parity signal | — | 1989-01-24 |