Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6266766 | Method and apparatus for increasing throughput when accessing registers by using multi-bit scoreboarding with a bypass control unit | — | 2001-07-24 |
| 6262658 | Tipping indicator | — | 2001-07-17 |
| 6237087 | Method and apparatus for speeding sequential access of a set-associative cache | — | 2001-05-22 |
| 6195230 | Disk head assembly with multiple read and/or write transducers for improved performance | — | 2001-02-27 |
| 6085012 | Planar waveguide and method of forming the same | — | 2000-07-04 |
| 6072808 | Method of providing and retrieving a data segment | — | 2000-06-06 |
| 5949942 | Planar waveguide and method of forming the same | — | 1999-09-07 |
| 5905902 | Programmable state machine employing a cache-like arrangement | — | 1999-05-18 |
| 5889975 | Method and apparatus permitting the use of a pipe stage having an unknown depth with a single microprocessor core | Paul Gilbert Meyer, Stephen Strazdus, Thomas Adelmeyer, Jay Heeb, Avery C. Topps | 1999-03-30 |
| 5848288 | Method and apparatus for accommodating different issue width implementations of VLIW architectures | — | 1998-12-08 |
| 5657475 | System for protecting memory accesses by comparing the upper and lower bounds addresses and attribute bits identifying unauthorized combinations of type of operation and mode of access | Byron R. Gillespie, Elliot Garbus, Mitchell Kahn, Thomas M. Johnson, Jay Heeb | 1997-08-12 |
| 5561782 | Pipelined cache system having low effective latency for nonsequential accesses | — | 1996-10-01 |
| 5513337 | System for protecting unauthorized memory accesses by comparing base memory address with mask bits and having attribute bits for identifying access operational mode and type | Byron R. Gillespie, Elliot Garbus, Mitchell Kahn, Thomas M. Johnson, Jay Heeb | 1996-04-30 |