DP

David I. Poisner

IN Intel: 111 patents #165 of 30,777Top 1%
WS Wake Forest University Health Sciences: 3 patents #66 of 318Top 25%
📍 Rancho Cordova, CA: #2 of 502 inventorsTop 1%
🗺 California: #1,728 of 386,348 inventorsTop 1%
Overall (All Time): #11,028 of 4,157,543Top 1%
114
Patents All Time

Issued Patents All Time

Showing 101–114 of 114 patents

Patent #TitleCo-InventorsDate
6014758 Method and apparatus for detecting and reporting failed processor reset 2000-01-11
6012154 Method and apparatus for detecting and recovering from computer system malfunction 2000-01-04
5991841 Memory transactions on a low pin count bus Andrew H. Gafken, Joseph A. Bennett 1999-11-23
5983354 Method and apparatus for indication when a bus master is communicating with memory Nima Homayoun, Sung-Soo Cho 1999-11-09
5943506 System for facilitating data I/O between serial bus input device and non-serial bus cognition application by generating alternate interrupt and shutting off interrupt triggering activities 1999-08-24
5890012 System for programming peripheral with address and direction information and sending the information through data bus or control line when DMA controller asserts data knowledge line 1999-03-30
5890004 Method and apparatus for signaling power management events between two devices 1999-03-30
5862387 Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller Neil W. Songer, James P. Kardach, Sung-Soo Cho, Jim S. Cheng, Debra T. Cohen +3 more 1999-01-19
5802269 Method and apparatus for power management of distributed direct memory access (DDMA) devices Rajesh Raman 1998-09-01
5761537 Method and apparatus for integrating three dimensional sound into a computer system having a stereo audio circuit Jay J. Sturges 1998-06-02
5729760 System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode 1998-03-17
5708815 DMA emulation via interrupt muxing 1998-01-13
5664197 Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller James P. Kardach, Sung-Soo Cho, Jim S. Cheng, Debra T. Cohen, John W. Horigan +3 more 1997-09-02
5652895 Computer system having a power conservation mode and utilizing a bus arbiter device which is operable to control the power conservation mode 1997-07-29