Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10430191 | Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption | Yevgeniy M. Astigeyevich, Dmitry M. Maslennikov, Sergey P. Scherbinin, Marat Zakirov, Pavel G. Matveyev +2 more | 2019-10-01 |
| 10241789 | Method to do control speculation on loads in a high performance strand-based loop accelerator | Alexander Y. Ostanevich, Sergey P. Scherbinin, Jayesh Iyer, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-26 |
| 10241794 | Apparatus and methods to support counted loop exits in a multi-strand loop processor | Sergey P. Scherbinin, Jayesh Iyer, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-26 |
| 10241801 | Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator | Jayesh Iyer, Sergey P. Scherbinin, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-26 |
| 10235171 | Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor | Alexander Y. Ostanevich, Jayesh Iyer, Sergey P. Scherbinin, Dmitry M. Maslennikov, Denis G. Motin +3 more | 2019-03-19 |
| 9086873 | Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture | Yevgeniy M. Astigeyevich, Dmitry M. Maslennikov, Sergey P. Scherbinin, Marat Zakirov, Pavel G. Matveyev +2 more | 2015-07-21 |