Issued Patents All Time
Showing 126–137 of 137 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9742603 | Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces | Chenchu Punnarao Bandi, Sabyasachi Mohapatra | 2017-08-22 |
| 9679097 | Selective power state table composition | — | 2017-06-13 |
| 9652351 | System to detect charger and remote host for type-C connector | Karthi R. Vadivelu | 2017-05-16 |
| 9628124 | Sensor signals interference mitigation method and apparatus | — | 2017-04-18 |
| 9606955 | Embedded universal serial bus solutions | Huimin Chen, Jia Jun Lee, Teong Guan Yew, Tim McKee | 2017-03-28 |
| 9606949 | Universal scalable system: on-the-fly system performance conversion via PC-on-a-card and USB for smart devices and IoT enabling | Khang Choong Yong, Khai Ern See, Jackson Chung Peng Kong, Teong Keat Beh, Eng Huat Goh | 2017-03-28 |
| 9601916 | Back power protection circuit | Karthik Ns, Raghavendra Devappa Sharma, Dharmaray M. Nedalgi, Prasad Bhilawadi | 2017-03-21 |
| 9455752 | Apparatus and method for adaptive common mode noise decomposition and tuning | Khang Choong Yong, Boon Ping Koh, Wil Choon Song | 2016-09-27 |
| 8943451 | Hierarchical finite state machine generation for power state behavior in an electronic design | Pankaj Kumar Dwivedi, Sachin Kakkar, Rudra Mukherjee | 2015-01-27 |
| 8689033 | Power supply and data signal interface circuit with overvoltage protection | Parul K. Sharma | 2014-04-01 |
| 8643425 | Level shifter circuit | Nidhi Chaudhry, Parul K. Sharma | 2014-02-04 |
| 7498848 | System and method for monitoring clock signal in an integrated circuit | Sanjay Wadhwa | 2009-03-03 |