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Prashant Shamarao, Chris DeMarco, Rohit Singhal, Alex Reed |
2014-04-01 |
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Old virtual queues technique for routing data packets in a packet switch |
Angus David Starr MacAdam |
2011-12-20 |
| 7974278 |
Packet switch with configurable virtual channels |
Angus David Starr MacAdam, Bruce Lorenz Chin |
2011-07-05 |
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Packet switch with configurable bandwidth allocation precision |
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Grid array microelectronic packages with increased periphery |
David Klein |
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Asynchronous FIFO increment and decrement control for interfaces that operate at differing clock frequencies |
Bruce C. Grugett |
2003-09-02 |
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Integrated circuit memory devices having control circuits therein that provide column redundancy capability |
— |
2002-04-16 |
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Priority encoding for FIFO memory devices that interface multiple ports to a data receiving device |
— |
2001-07-24 |
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Pass gate decoder for a multiport memory dEvice that uses a single ported memory cell array structure |
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1998-12-08 |