Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9594720 | Interface between a bus and a inter-thread interconnect | Andrew STANFORD-JASON, Nigel Toon, Daniel John Pelham Wilkinson | 2017-03-14 |
| 9367321 | Processor instruction set for controlling an event source to generate events used to schedule threads | — | 2016-06-14 |
| 8966488 | Synchronising groups of threads with dedicated hardware logic | Peter Hedinger, Alastair Dixon | 2015-02-24 |
| 8898438 | Processor architecture for use in scheduling threads in response to communication activity | — | 2014-11-25 |
| 8347312 | Thread communications | Peter Hedinger, Alastair Dixon | 2013-01-01 |
| 8224884 | Processor communication tokens | — | 2012-07-17 |
| 8219789 | Interface processor | — | 2012-07-10 |
| 8185719 | Message routing scheme for an array having a switch with address comparing component and message routing component | — | 2012-05-22 |
| 8185722 | Processor instruction set for controlling threads to respond to events | — | 2012-05-22 |
| 8139601 | Token protocol | — | 2012-03-20 |
| 7962717 | Message routing scheme | — | 2011-06-14 |
| 7958333 | Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected | — | 2011-06-07 |
| 7948060 | Integrated circuit structure | Ken Williamson, Simon Christopher Dequin Clemow | 2011-05-24 |
| 7676653 | Compact instruction set encoding | — | 2010-03-09 |
| 7617386 | Scheduling thread upon ready signal set when port transfers data on trigger time activation | Peter Hedinger, Alastair Dixon | 2009-11-10 |
| 7613909 | Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor | Peter Hedinger, Alastair Dixon | 2009-11-03 |
| 6757759 | Microcomputer chips with interconnected address and data paths | Andrew Michael Jones | 2004-06-29 |
| 6697931 | System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry | Andrew Michael Jones | 2004-02-24 |
| 6694407 | Cache memory with data transfer control and method of operating same | Hendrik Muller | 2004-02-17 |
| 6658514 | Interrupt and control packets for a microcomputer | Andrew Michael Jones | 2003-12-02 |
| 6564314 | Computer instruction compression | Andrew Sturges, Nathan Mackenzie Sidwell | 2003-05-13 |
| 6549965 | Microcomputer with interrupt packets | Andrew Michael Jones | 2003-04-15 |
| 6449670 | Microcomputer with bit packets for interrupts, control and memory access | Andrew Michael Jones | 2002-09-10 |
| 6415344 | System and method for on-chip communication | Andrew Michael Jones | 2002-07-02 |
| 6414368 | Microcomputer with high density RAM on single chip | Jonathan Edwards, David L. Waller | 2002-07-02 |