Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8872689 | Circuit arrangement and method for operating an analog-to-digital converter | Alexander Mayer | 2014-10-28 |
| 7180805 | Differental current source for generating DRAM refresh signal | Andre Schaefer | 2007-02-20 |
| 7136320 | Method and regulating circuit for refreshing dynamic memory cells | Michael Hausmann | 2006-11-14 |
| 7068079 | Circuit device with clock pulse detection facility | Andre Schaefer, Johann Pfeiffer, Kasimierz Szczypinski | 2006-06-27 |
| 7049930 | Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement | Andre Schaefer, Xaver Obergrussberger, Sebastian Mosler | 2006-05-23 |
| 6870420 | Method of increasing an internal operating voltage for an integrated circuit, and integrated circuit | Michael Hausmann | 2005-03-22 |
| 6850099 | Scalable driver device and related integrated circuit | Bernd Klehn, Ralf Klein | 2005-02-01 |
| 6850448 | Temperature-dependent refresh cycle for DRAM | Michael Sommer | 2005-02-01 |
| 6833745 | Signal generator for charge pump in an integrated circuit | Michael Hausmann | 2004-12-21 |
| 6809980 | Limiter for refresh signal period in DRAM | Michael Hausmann | 2004-10-26 |
| 6737895 | Control signal generating device for driving a plurality of circuit units | Bernd Klehn, Andrea Zuckerstatter, Ralf Klein | 2004-05-18 |
| 6721214 | Drive circuit and control method | Michael Hausmann | 2004-04-13 |
| 6700426 | Programmable voltage pump having a ground option | Martin Brox, Bernd Klehn | 2004-03-02 |
| 6690605 | Logic signal level converter circuit and memory data output buffer using the same | Andre Schäfer | 2004-02-10 |
| 6545930 | Integrated memory having a voltage regulating circuit | Helmut Fischer | 2003-04-08 |
| 6477106 | Circuit configuration for deactivating word lines in a memory matrix | Helmut Fischer | 2002-11-05 |
| 6456553 | Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration | Eckhard Brass, Thoai-Thai Le, Jürgen Lindolf | 2002-09-24 |
| 6370069 | Method for testing a multiplicity of word lines of a semiconductor memory configuration | Eckhard Brass, Thilo Schaffroth, Helmut Schneider | 2002-04-09 |