Issued Patents All Time
Showing 51–65 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6546469 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6546470 | Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-04-08 |
| 6539487 | System for dynamically selecting maximum number of accessible banks of memory per cycle by monitoring actual power to each of the banks to determine the number of accessible banks | James Stephen Fields, Jr., Praveen S. Reddy | 2003-03-25 |
| 6532519 | Apparatus for associating cache memories with processors within a multiprocessor data processing system | Ravi Kumar Arimilli, James Stephen Fields, Jr., Jody B. Joyner | 2003-03-11 |
| 6467030 | Method and apparatus for forwarding data in a hierarchial cache memory architecture | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Praveen S. Reddy | 2002-10-15 |
| 6442653 | Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-08-27 |
| 6408362 | Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-06-18 |
| 6405290 | Multiprocessor system bus protocol for O state memory-consistent data | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-06-11 |
| 6397303 | Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-05-28 |
| 6356982 | Dynamic mechanism to upgrade o state memory-consistent cache lines | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-03-12 |
| 6349368 | High performance mechanism to support O state horizontal cache-to-cache transfers | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-02-19 |
| 6345341 | Method of cache management for dynamically disabling O state memory-consistent data | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-02-05 |
| 6338116 | Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2002-01-08 |
| 6298416 | Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Praveen S. Reddy | 2001-10-02 |
| 6282615 | Multiprocessor system bus with a data-less castout mechanism | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr. | 2001-08-28 |