Issued Patents All Time
Showing 101–125 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10713051 | Replacing table of contents (TOC)-setting instructions in code with TOC predicting instructions | Valentina Salapura | 2020-07-14 |
| 10705973 | Initializing a data structure for use in predicting table of contents pointer values | Valentina Salapura | 2020-07-07 |
| 10705841 | Instruction to perform a logical operation on conditions and to quantize the Boolean result of that operation | Brett Olsson | 2020-07-07 |
| 10698686 | Configurable architectural placement control | Valentina Salapura | 2020-06-30 |
| 10698688 | Efficient quantization of compare results | Brett Olsson | 2020-06-30 |
| 10691453 | Vector load with instruction-specified byte count less than a vector size for big and little endian processing | Brett Olsson | 2020-06-23 |
| 10691456 | Vector store instruction having instruction-specified byte count to be stored supporting big and little endian processing | Brett Olsson | 2020-06-23 |
| 10691590 | Affinity domain-based garbage collection | Zhong Liang Wang | 2020-06-23 |
| 10691600 | Table of contents cache entry having a pointer for a range of addresses | Valentina Salapura | 2020-06-23 |
| 10684853 | Employing prefixes to control floating point operations | Valentina Salapura | 2020-06-16 |
| 10684852 | Employing prefixes to control floating point operations | Valentina Salapura | 2020-06-16 |
| 10671397 | Reduced save and restore instructions for call-clobbered registers | Ulrich Weigand | 2020-06-02 |
| 10671393 | Techniques for facilitating cracking and fusion within a same instruction group | Valentina Salapura | 2020-06-02 |
| 10671386 | Compiler controls for program regions | Valentina Salapura | 2020-06-02 |
| 10671387 | Vector memory access instructions for big-endian element ordered and little-endian element ordered computer code and data | Brett Olsson | 2020-06-02 |
| 10664181 | Protecting in-memory configuration state registers | Valentina Salapura | 2020-05-26 |
| 10657059 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Christian Jacobi, Chung-Lung K. Shum | 2020-05-19 |
| 10656946 | Predicting a table of contents pointer value responsive to branching to a subroutine | Valentina Salapura | 2020-05-19 |
| 10649785 | Tracking changes to memory via check and recovery | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2020-05-12 |
| 10642757 | Single call to perform pin and unpin operations | Valentina Salapura | 2020-05-05 |
| 10642586 | Compiler optimizations for vector operations that are reformatting-resistant | William J. Schmidt | 2020-05-05 |
| 10635602 | Address translation prior to receiving a storage reference using the address to be translated | Valentina Salapura | 2020-04-28 |
| 10635592 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Christian Jacobi, Chung-Lung K. Shum | 2020-04-28 |
| 10635441 | Caller protected stack return address in a hardware managed stack architecture | Karl J. Duvalsaint, Valentina Salapura | 2020-04-28 |
| 10621095 | Processing data based on cache residency | Timothy J. Slegel | 2020-04-14 |