Issued Patents All Time
Showing 51–75 of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8436677 | Structure for a reference voltage generator for analog to digital converters | Lukas Kull | 2013-05-07 |
| 8421573 | Inductor combining primary and secondary coils with phase shifting | Marcel A. Kossel, Thomas Morf, Jonas R. Weiss | 2013-04-16 |
| 8234540 | Error correcting code protected quasi-static bit communication on a high-speed bus | Peter Buchmann, Kevin C. Gower, Robert J. Reese, Michael R. Trombley | 2012-07-31 |
| 8170157 | Low jitter communication system | Christian I. Menolfi, Thomas H. Toifl | 2012-05-01 |
| 8149979 | Method and apparatus for handling of clock information in serial link ports | Peter Buchmann | 2012-04-03 |
| 8139430 | Power-on initialization and test for a cascade interconnect memory system | Peter Buchmann, Frank D. Ferraiolo, Kevin C. Gower, Robert J. Reese, Eric E. Retter +3 more | 2012-03-20 |
| 8130887 | Method and arrangements for link power reduction | Hayden C. Cranford, Jr., Gareth John Nicholls, Vernon R. Norman, Karl D. Selander, Michael A. Sorna | 2012-03-06 |
| 8093910 | Cross-talk processing in serial link buses | Thomas H. Toifl | 2012-01-10 |
| 8054867 | Apparatus for transmitting data and additional information simultaneously within a wire-based communication system | Hayden C. Cranford, Jr. | 2011-11-08 |
| 8054926 | Clock and data recovery system and method for clock and data recovery based on a forward error correction | Hayden C. Cranford, Jr., Thomas H. Toifl | 2011-11-08 |
| 8044732 | Continuously tunable inductor and method to continuously tune an inductor | Marcel A. Kossel, Thomas Morf, Jonas R. Weiss | 2011-10-25 |
| 8018312 | Inductor and method of operating an inductor by combining primary and secondary coils with coupling structures | Marcel A. Kossel, Thomas Morf, Jonas R. Weiss | 2011-09-13 |
| 7934115 | Deriving clocks in a memory system | Frank D. Ferraiolo, Kevn C. Gower | 2011-04-26 |
| 7885365 | Low-power, low-area high-speed receiver architecture | Christoph Hagleitner, Christian I. Menolfi, Thomas H. Toifl | 2011-02-08 |
| 7839221 | Phase locked loop and method for adjusting the frequency and phase in the phase locked loop | Marcel A. Kossel, Thomas Morf, Silvan Wehrli | 2010-11-23 |
| 7816747 | Detector for detecting electromagnetic waves | Thomas Morf, Jonas R. Weiss | 2010-10-19 |
| 7809054 | One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery | Juan-Antonio Carballo, Hayden C. Cranford, Jr., Gareth John Nicholls, Vernon R. Norman | 2010-10-05 |
| 7783439 | Signal generator device and data eye scan system | Marcel A. Kossel | 2010-08-24 |
| 7692447 | Driver circuit | Hayden C. Cranford, Jr., Christian I. Menolfi, Thomas H. Toifl | 2010-04-06 |
| 7684534 | Method and apparatus for handling of clock information in serial link ports | Peter Buchmann | 2010-03-23 |
| 7679459 | Multiphase signal generator | Christian I. Menolfi, Thomas H. Toifl | 2010-03-16 |
| 7661052 | Using statistical signatures for testing high-speed circuits | Hayden C. Cranford, Jr., Vernon R. Norman | 2010-02-09 |
| 7646839 | Unified digital architecture | Hayden C. Cranford, Jr., Vernon R. Norman | 2010-01-12 |
| 7539243 | Method and system for low-power integrating decision feedback equalizer with fast switched-capacitor feed forward path | Thomas H. Toifl, Christian I. Menolfi | 2009-05-26 |
| 7522687 | Clock and data recovery system and method for clock and data recovery based on a forward error correction | Hayden C. Cranford, Jr., Thomas H. Toifl | 2009-04-21 |