Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6067603 | Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect | Gary Dale Carpenter, David B. Glasco | 2000-05-23 |
| 5898857 | Method and system for interfacing an upgrade processor to a data processing system | Daniel Paul Beaman, Gary Dale Carpenter, Wendel Glenn Voigt | 1999-04-27 |
| 5768550 | Bus interface logic system | Thoi Nguyen | 1998-06-16 |
| 5603041 | Method and system for reading from a m-byte memory utilizing a processor having a n-byte data bus | Gary Dale Carpenter | 1997-02-11 |
| 5553276 | Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units | — | 1996-09-03 |
| 5548746 | Non-contiguous mapping of I/O addresses to use page protection of a process | Gary Dale Carpenter, Marc R. Faucher, James C. Peterson, Howard Carl Tanner | 1996-08-20 |
| 5544342 | System and method for prefetching information in a processing system | — | 1996-08-06 |
| 5450559 | Microcomputer system employing address offset mechanism to increase the supported cache memory capacity | Ralph M. Begun, Patrick M. Bland | 1995-09-12 |
| 5448521 | Connecting a short word length non-volatile memory to a long word length address/data multiplexed bus | Sean Eugene Curry, Marc R. Faucher, James C. Peterson, Howard Carl Tanner | 1995-09-05 |
| 5327545 | Data processing apparatus for selectively posting write cycles using the 82385 cache controller | Ralph M. Begun, Patrick M. Bland | 1994-07-05 |
| 5175826 | Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 | Ralph M. Begun, Patrick M. Bland | 1992-12-29 |
| 5170481 | Microprocessor hold and lock circuitry | Ralph M. Begun, Patrick M. Bland | 1992-12-08 |
| 5129090 | System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration | Patrick M. Bland, Philip E. Milling | 1992-07-07 |
| 5125084 | Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller | Ralph M. Begun, Patrick M. Bland | 1992-06-23 |
| 5107507 | Bidirectional buffer with latch and parity capability | Patrick M. Bland, Gene J. Gaudenzi, Kevin G. Kramer, Susan L. Tempest | 1992-04-21 |
| 5045998 | Method and apparatus for selectively posting write cycles using the 82385 cache controller | Ralph M. Begun, Patrick M. Bland | 1991-09-03 |
| 5034917 | Computer system including a page mode memory with decreased access time and method of operation thereof | Patrick M. Bland | 1991-07-23 |
| 4598356 | Data processing system including a main processor and a co-processor and co-processor error handling logic | Dennis Moeller | 1986-07-01 |
| 4575826 | Refresh generator system for a dynamic memory | — | 1986-03-11 |
| 4528626 | Microcomputer system with bus control means for peripheral processing devices | Dennis Moeller | 1985-07-09 |
| 4442428 | Composite video color signal generation from digital color signals | David A. Kummer, Jesus A. Saenz | 1984-04-10 |
| 4437092 | Color video display system having programmable border color | Lewis C. Eggebrecht, David A. Kummer, Jesus A. Saenz | 1984-03-13 |